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ds05-50310-2e fujitsu semiconductor data sheet stacked mcp (multi-chip package) flash memory & fcram cmos 64 m ( 16) flash memory & 32 m ( 16) mobile fcram tm mb84vd23481fj -70 n features ? power supply voltage of 2.7 v to 3.1 v ? high performance 70 ns maximum access time (flash) 70 ns maximum access time (fcram) ? operating temperature - 30 c to + 85 c ? package 65 - ball fbga (continued) n product line-up *: both v cc f and v cc r must be the same level when either part is being accessed. n pac k ag e flash memory fcram power supply voltage ( v ) v cc f* = 2.7 v to 3.1 v v cc r* = 2.7 v to 3.1 v max address access time (ns) 70 65 max ce access time (ns) 70 65 max oe access time (ns) 30 40 65-ball plastic fbga (bga-65p-m01)
mb84vd23481fj- 70 2 (continued) flash memory ?0.17 m m m m m process technology ? simultaneous read / write operations ( dual bank ) ? flexbank tm * 1 bank a : 8 mbit (8 kb 8 and 64 kb 15) bank b : 24 mbit (64 kb 48) bank c : 24 mbit (64 kb 48) bank d : 8 mbit (8 kb 8 and 64 kb 15) two virtual banks are chosen from the combination of four physical banks. host system can program or erase in one bank, and then read immediately and simultaneously from the other bank with zero latency between read and write operations. read-while-erase read-while-program ? single 3.0 v read , program , and erase minimized system level power requirements ? minimum 100,000 program / erase cycles ? sector erase architecture sixteen 4 kword and one hundred twenty-six 32 kword sectors in word. any combination of sectors can be concurrently erased. it also supports full chip erase. ? hiddenrom region 256 byte of hiddenrom, accessible through a new hiddenrom enable command sequence factory serialized and protected to provide a secure electronic serial number (esn) ? wp / acc input pin at v il , allows protection of outermost 2 8 kbytes on both ends of boot sectors, regardless of sector protection/ unprotection status at v ih , allows removal of boot sector protection at v acc , increases program performance ? embedded erase tm * 2 algorithms automatically preprograms and erases the chip or any sector ? embedded program tm * 2 algorithms automatically writes and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ? ready / busy output ( ry / by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, the device automatically switches itself to low power mode. ? low v cc f write inhibit 2.5 v ? program suspend / resume suspends the program operation to allow a read in another byte ? erase suspend / resume suspends the erase operation to allow a read data and/or program in another sector within the same device ? please refer to mbm29dl64df datasheet in detailed function (continued)
mb84vd23481fj- 70 3 (continued) fcram tm * 3 ? power dissipation operating : 25 ma max standby : 100 m a max ? power down mode sleep : 10 m a max nap : 60 m a max 8m partial : 70 m a max ? power down control by ce2r ? byte write control: lb (dq 7 to dq 0 ), ub (dq 15 to dq 8 ) ? 8 words address access capability *1 : flexbank tm is a trademark of fujitsu limited, japan. *2 : embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc. *3 : fcram tm is a trademark of fujitsu limited, japan.
mb84vd23481fj- 70 4 n pin assignment fbga (top view) marking side (bga-65p-m01) d8 a 13 d7 a 9 d6 a 20 d5 ry/by d4 a 18 d3 a 5 d2 a 2 d9 a21 f8 f7 dq 6 dq 1 f3 v ss f2 a 0 f9 a 16 g8 dq 15 g7 dq 13 g6 dq 4 g5 dq 3 g4 dq 9 g3 oe g2 cef g9 e8 a 14 e7 a 10 e4 a 17 e3 a 4 e2 a 1 e9 pe h8 dq 7 h7 dq 12 h6 vccr h5 vccf vccf h4 dq 10 h3 dq 0 h2 ce1r h9 vss j8 dq 14 j7 dq 5 j6 j5 dq 11 j4 dq 2 j3 dq 8 k9 n.c. n.c. n.c. k2 n.c. k1 n.c. k10 n.c. c8 a 12 c7 a 19 c6 ce2r c5 reset c4 ub c3 a 6 c2 a 3 c9 a 15 b8 a 11 b7 a 8 b6 we b5 wp/acc b4 lb b3 a 7 a9 n.c. b1 n.c. a10 n.c. a2 n.c. a1 n.c. f4
mb84vd23481fj- 70 5 n pin description n block diagram pin name function input/output a 20 to a 0 address inputs (common) i a 21 address input (flash) i dq 15 to dq 0 data inputs/outputs (common) i/o ce f chip enable (flash) i ce1 r chip enable (fcram) i ce2r chip enable (fcram) i oe output enable (common) i we write enable (common) i ry/by ready/busy outputs (flash) open drain output o ub upper byte control (fcram) i lb lower byte control (fcram) i reset hardware reset pin/sector protection unlock (flash) i wp /acc write protect/acceleration (flash) i pe partial enable (fcram) i n.c. no internal connection ? v ss device ground (common) power v cc f device power supply (flash) power v cc r device power supply (fcram) power v ss v cc r 64 m bit reset flash memory we 32 m bit fcram ce f a 21 to a 0 oe ce1 r v ss v cc f a 21 to a 0 a 20 to a 0 dq 15 to dq 0 ry/by lb ub wp /acc ce2r dq 15 to dq 0 dq 15 to dq 0 pe
mb84vd23481fj- 70 6 n device bus operations legend: l = v il , h = v ih , x = v il or v ih . see dc characteristics for voltage levels. *1 : other operations except for indicated this column are prohibited. *2 : do not apply ce f = v il , ce1 r = v il and ce2r = v ih all at once. *3 : fcram output disable condition should not be kept longer than 1 ms. *4 : we can be v il if oe is v il , oe at v ih initiates the write operations. *5 : fcram lb ,ub control at read operation is not supported. *6 : it is also used for the extended sector group protections. *7 : the fcram power down program can be performed one time after compliance of power-up timings and it should not be re-programmed after regular read or write. *8 : fcram power down mode can be entered from standby state and all dq pins are in high-z state. i pd r current and data retention depends on the selection of power down program. *9 : either or both lb and ub must be low for fcram read operation. *10 : can be either v il or v ih but must be valid before read or write. *11 : see fcram power down program key table . *12 : protect outer most 2x8k bytes ( 4 words ) on both ends of the boot block sectors. operation * 1, * 2 ce f ce1 rce2r oe we lb ub pe a 21 to a 0 dq 7 to dq 0 dq 15 to dq 8 reset wp / acc* 12 full standby h h h x x x x h x high-z high-z h x output disable * 3 hl hhhxxhx * 10 high-z high-z h x l h h h h x x h x high-z high-z h x read from flash * 4 l h h l h x x h vaild d out d out hx write to flash l h h h l x x h vaild d in d in hx read from fcram * 5 hl hlhl* 9 l* 9 h vaild d out d out hx write to fcram h l h h l ll h vaild d in d in hx h l high-z d in lh d in high-z temporary sector group unprotection* 6 xx xxxx xx x x x v id x flash hardware reset x h h x x x x x x high-z high-z l x boot block sector write protection xx xxxx xx x x x x l fcram power down program * 7 h h h x x x x l key* 11 high-z high-z h x fcram no read h l h l h h h h vaild high-z high-z h x fcram power down * 8 xx l xxx xx x x x x x
mb84vd23481fj- 70 7 n 64m frash memory characteristics for mcp 1. flexible sector-erase architecture on flash memory ? sixteen 4k words, and one hundred twenty-six 32 k words. ? individual-sector, multiple-sector, or bulk-erase capability. sector architecture sa31 : 64kb (32kw) sa30 : 64kb (32kw) sa29 : 64kb (32kw) sa28 : 64kb (32kw) sa27 : 64kb (32kw) sa26 : 64kb (32kw) sa25 : 64kb (32kw) sa24 : 64kb (32kw) sa23 : 64kb (32kw) sa22 : 64kb (32kw) sa21 : 64kb (32kw) sa20 : 64kb (32kw) sa19 : 64kb (32kw) sa18 : 64kb (32kw) sa17 : 64kb (32kw) sa16 : 64kb (32kw) sa15 : 64kb (32kw) sa14 : 64kb (32kw) sa13 : 64kb (32kw) sa12 : 64kb (32kw) sa11 : 64kb (32kw) sa10 : 64kb (32kw) sa9 : 64kb (32kw) sa8 : 64kb (32kw) sa7 : 8kb (4kw) sa6 : 8kb (4kw) sa5 : 8kb (4kw) sa4 : 8kb (4kw) sa3 : 8kb (4kw) sa2 : 8kb (4kw) sa70 : 64kb (32kw) sa69 : 64kb (32kw) sa68 : 64kb (32kw) sa67 : 64kb (32kw) sa66 : 64kb (32kw) sa65 : 64kb (32kw) sa64 : 64kb (32kw) sa63 : 64kb (32kw) sa62 : 64kb (32kw) sa61 : 64kb (32kw) sa60 : 64kb (32kw) sa59 : 64kb (32kw) sa58 : 64kb (32kw) sa57 : 64kb (32kw) sa56 : 64kb (32kw) sa55 : 64kb (32kw) sa54 : 64kb (32kw) sa53 : 64kb (32kw) sa52 : 64kb (32kw) sa51 : 64kb (32kw) sa50 : 64kb (32kw) sa49 : 64kb (32kw) sa48 : 64kb (32kw) sa47 : 64kb (32kw) sa46 : 64kb (32kw) sa45 : 64kb (32kw) sa44 : 64kb (32kw) sa43 : 64kb (32kw) sa42 : 64kb (32kw) sa41 : 64kb (32kw) sa40 : 64kb (32kw) sa39 : 64kb (32kw) sa38 : 64kb (32kw) sa37 : 64kb (32kw) sa36 : 64kb (32kw) sa35 : 64kb (32kw) sa34 : 64kb (32kw) sa33 : 64kb (32kw) sa32 : 64kb (32kw) sa1 : 8kb (4kw) sa0 : 8kb (4kw) bank a bank b 070000h 078000h 060000h 068000h 050000h 058000h 040000h 048000h 030000h 038000h 020000h 028000h 010000h 018000h 007000h 008000h 005000h 006000h 003000h 004000h 001000h 002000h 000000h sa102 : 64kb (32kw) sa101 : 64kb (32kw) sa100 : 64kb (32kw) sa99 : 64kb (32kw) sa98 : 64kb (32kw) sa97 : 64kb (32kw) sa96 : 64kb (32kw) sa95 : 64kb (32kw) sa94 : 64kb (32kw) sa93 : 64kb (32kw) sa92 : 64kb (32kw) sa91 : 64kb (32kw) sa90 : 64kb (32kw) sa89 : 64kb (32kw) sa88 : 64kb (32kw) sa87 : 64kb (32kw) sa86 : 64kb (32kw) sa85 : 64kb (32kw) sa84 : 64kb (32kw) sa83 : 64kb (32kw) sa82 : 64kb (32kw) sa81 : 64kb (32kw) sa80 : 64kb (32kw) sa79 : 64kb (32kw) sa78 : 64kb (32kw) sa77 : 64kb (32kw) sa76 : 64kb (32kw) sa75 : 64kb (32kw) sa74 : 64kb (32kw) sa73 : 64kb (32kw) 3fffffh sa141 : 8kb (4kw) sa140 : 8kb (4kw) sa139 : 8kb (4kw) sa138 : 8kb (4kw) sa137 : 8kb (4kw) sa136 : 8kb (4kw) sa135 : 8kb (4kw) sa134 : 8kb (4kw) sa133 : 64kb (32kw) sa132 : 64kb (32kw) sa131 : 64kb (32kw) sa130 : 64kb (32kw) sa129 : 64kb (32kw) sa128 : 64kb (32kw) sa127 : 64kb (32kw) sa126 : 64kb (32kw) sa125 : 64kb (32kw) sa124 : 64kb (32kw) sa123 : 64kb (32kw) sa122 : 64kb (32kw) sa121 : 64kb (32kw) sa120 : 64kb (32kw) sa119 : 64kb (32kw) sa118 : 64kb (32kw) sa117 : 64kb (32kw) sa116 : 64kb (32kw) sa115 : 64kb (32kw) sa114 : 64kb (32kw) sa113 : 64kb (32kw) sa112 : 64kb (32kw) sa111 : 64kb (32kw) sa110 : 64kb (32kw) sa109 : 64kb (32kw) sa108 : 64kb (32kw) sa107 : 64kb (32kw) sa106 : 64kb (32kw) sa105 : 64kb (32kw) sa104 : 64kb (32kw) sa103 : 64kb (32kw) sa72 : 64kb (32kw) sa71 : 64kb (32kw) bank c bank d 3ff000h 3fe000h 3fd000h 3fc000h 3fb000h 3fa000h 3f9000h 0f0000h 0f8000h 0e0000h 0e8000h 0d0000h 0d8000h 0c0000h 0c8000h 0b0000h 0b8000h 0a0000h 0a8000h 090000h 098000h 088000h 080000h 170000h 178000h 160000h 168000h 150000h 158000h 140000h 148000h 130000h 138000h 120000h 128000h 110000h 118000h 100000h 108000h 1f0000h 1f8000h 1e0000h 1e8000h 1d0000h 1d8000h 1c0000h 1c8000h 1b0000h 1b8000h 1a0000h 1a8000h 190000h 198000h 188000h 180000h 270000h 278000h 260000h 268000h 250000h 258000h 240000h 248000h 230000h 238000h 220000h 228000h 210000h 218000h 208000h 2f0000h 2f8000h 2e0000h 2e8000h 2d0000h 2d8000h 2c0000h 2c8000h 2b0000h 2b8000h 2a0000h 2a8000h 290000h 298000h 288000h 280000h 370000h 378000h 360000h 368000h 350000h 358000h 340000h 348000h 330000h 338000h 320000h 328000h 310000h 318000h 300000h 308000h 3f0000h 3f8000h 3e0000h 3e8000h 3d0000h 3d8000h 3c0000h 3c8000h 3b0000h 3b8000h 3a0000h 3a8000h 390000h 398000h 388000h 380000h 200000h 1fffffh word mode word mode
mb84vd23481fj- 70 8 flexbank tm architecture example of virtual banks combination note : when multiple sector erase over several banks is operated, the system cannot read out of the bank to which a sector being erased belongs. for example, suppose that erasing is taking place at both bank a and bank b, neither bank a nor bank b is read out (they would output the sequence flag once they were selected.) meanwhile the system would get to read from either bank c or bank d. simultaneous operation * : by writing erase suspend command on the bank address of sector being erased, the erase operation gets suspended so that it enables reading from or programming the remaining sectors. note: bank 1 and bank 2 are divided for the sake of convenience at simultaneous operation. actually, the bank consists of 4 banks, bank a, bank b, bank c and bank d. bank address (ba) meant to specify each of the banks. bank splits bank 1 bank 2 volume combination volume combination 1 8 mbit bank a 56 mbit remainder (bank b, c, d) 2 24 mbit bank b 40 mbit remainder (bank a, c, d) 3 24 mbit bank c 40 mbit remainder (bank a, b, d) 4 8 mbit bank d 56 mbit remainder (bank a, b, c) bank splits bank 1 bank 2 volume combination sector size volume combination sector size 18 mbit bank a 8 8 kbyte/4 kword + 15 64 kbyte/32 kword 56 mbit bank b + bank c + bank d 8 8 kbyte/4 kword + 111 64 kbyte/32 kword 216 mbit bank a + bank d 16 8 kbyte/4 kword + 30 64 kbyte/32 kword 48 mbit bank b + bank c 96 64 kbyte/32 kword 3 24 mbit bank b 48 64 kbyte/32 kword 40 mbit bank a + bank c + bank d 16 8 kbyte/4 kword + 78 64 kbyte/32 kword 432 mbit bank a + bank b 8 8 kbyte/4 kword + 63 64 kbyte/32 kword 32 mbit bank c + bank d 8 8 kbyte/4 kword + 63 64 kbyte/32 kword case bank 1 status bank 2 status 1 read mode read mode 2 read mode autoselect mode 3 read mode program mode 4 read mode erase mode * 5 autoselect mode read mode 6 program mode read mode 7 erase mode * read mode
mb84vd23481fj- 70 9 sector address tables (continued) bank sector sector address address range bank address word mode a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank a sa0 0000000000 000000h to 000fffh sa1 0000000001 001000h to 001fffh sa2 0000000010 002000h to 002fffh sa3 0000000011 003000h to 003fffh sa4 0000000100 004000h to 004fffh sa5 0000000101 005000h to 005fffh sa6 0000000110 006000h to 006fffh sa7 0000000111 007000h to 007fffh sa8 0000001xxx 00 8000h to 00ffffh sa9 0000010xxx 010000h to 017fffh sa10 0000011xxx 01 8000h to 01ffffh sa11 0000100xxx 020000h to 027fffh sa12 0000101xxx 02 8000h to 02ffffh sa13 0000110xxx 030000h to 037fffh sa14 0000111xxx 03 8000h to 03ffffh sa15 0001000xxx 040000h to 047fffh sa16 0001001xxx 04 8000h to 04ffffh sa17 0001010xxx 050000h to 057fffh sa18 0001011xxx 05 8000h to 05ffffh sa19 0001100xxx 060000h to 067fffh sa20 0001101xxx 06 8000h to 06ffffh sa21 0001110xxx 070000h to 077fffh sa22 0001111xxx 07 8000h to 07ffffh
mb84vd23481fj- 70 10 (continued) (continued) bank sector sector address address range bank address word mode a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank b sa23 0010000xxx 080000h to 087fffh sa24 0010001xxx 08 8000h to 08ffffh sa25 0010010xxx 090000h to 097fffh sa26 0010011xxx 09 8000h to 09ffffh sa27 0010100xxx 0a0000h to 0a7fffh sa28 0010101xxx 0a 8000h to 0affffh sa29 0010110xxx 0b0000h to 0b7fffh sa30 0010111xxx 0b 8000h to 0bffffh sa31 0011000xxx 0c0000h to 0c7 fffh sa32 0011001xxx 0c 8000h to 0cffffh sa33 0011010xxx 0d0000h to 0d7 fffh sa34 0011011xxx 0d 8000h to 0dffffh sa35 0011100xxx 0e0000h to 0e7fffh sa36 0011101xxx 0e 8000h to 0effffh sa37 0011110xxx 0f0000h to 0f7fffh sa38 0011111xxx 0f 8000h to 0fffffh sa39 0100000xxx 100000h to 107fffh sa40 0100001xxx 10 8000h to 10ffffh sa41 0100010xxx 110000h to 117fffh sa42 0100011xxx 11 8000h to 11ffffh sa43 0100100xxx 120000h to 127fffh sa44 0100101xxx 12 8000h to 12ffffh sa45 0100110xxx 130000h to 137fffh sa46 0100111xxx 13 8000h to 13ffffh sa47 0101000xxx 140000h to 147fffh sa48 0101001xxx 14 8000h to 14ffffh sa49 0101010xxx 150000h to 157fffh sa50 0101011xxx 15 8000h to 15ffffh sa51 0101100xxx 160000h to 167fffh sa52 0101101xxx 16 8000h to 16ffffh sa53 0101110xxx 170000h to 177fffh sa54 0101111xxx 17 8000h to 17ffffh sa55 0110000xxx 180000h to 187fffh sa56 0110001xxx 18 8000h to 18ffffh sa57 0110010xxx 190000h to 197fffh sa58 0110011xxx 19 8000h to 19ffffh sa59 0110100xxx 1a0000h to 1a7fffh sa60 0110101xxx 1a 8000h to 1affffh sa61 0110110xxx 1b0000h to 1b7fffh sa62 0110111xxx 1b 8000h to 1bffffh sa63 0111000xxx 1c0000h to 1c7 fffh sa64 0111001xxx 1c 8000h to 1cffffh sa65 0111010xxx 1d0000h to 1d7 fffh sa66 0111011xxx 1d 8000h to 1dffffh sa67 0111100xxx 1e0000h to 1e7fffh sa68 0111101xxx 1e 8000h to 1effffh sa69 0111110xxx 1f0000h to 1f7fffh sa70 0111111xxx 1f 8000h to 1fffffh
mb84vd23481fj- 70 11 (continued) (continued) bank sector sector address address range bank address word mode a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank c sa71 1000000xxx 200000h to 207fffh sa72 1000001xxx 20 8000h to 20ffffh sa73 1000010xxx 210000h to 217fffh sa74 1000011xxx 21 8000h to 21ffffh sa75 1000100xxx 220000h to 227fffh sa76 1000101xxx 22 8000h to 22ffffh sa77 1000110xxx 230000h to 237fffh sa78 1000111xxx 23 8000h to 23ffffh sa79 1001000xxx 240000h to 247fffh sa80 1001001xxx 24 8000h to 24ffffh sa81 1001010xxx 250000h to 257fffh sa82 1001011xxx 25 8000h to 25ffffh sa83 1001100xxx 260000h to 267fffh sa84 1001101xxx 26 8000h to 26ffffh sa85 1001110xxx 270000h to 277fffh sa86 1001111xxx 27 8000h to 27ffffh sa87 1010000xxx 280000h to 287fffh sa88 1010001xxx 28 8000h to 28ffffh sa89 1010010xxx 290000h to 297fffh sa90 1010011xxx 29 8000h to 29ffffh sa91 1010100xxx 2a0000h to 2a7fffh sa92 1010101xxx 2a 8000h to 2affffh sa93 1010110xxx 2b0000h to 2b7fffh sa94 1010111xxx 2b 8000h to 2bffffh sa95 1011000xxx 2c0000h to 2c7 fffh sa96 1011001xxx 2c 8000h to 2cffffh sa97 1011010xxx 2d0000h to 2d7 fffh sa98 1011011xxx 2d 8000h to 2dffffh sa99 1011100xxx 2e0000h to 2e7fffh sa1001011101xxx 2e 8000h to 2effffh sa1011011110xxx 2f0000h to 2f7fffh sa1021011111xxx 2f 8000h to 2fffffh sa1031100000xxx 300000h to 307fffh sa1041100001xxx 30 8000h to 30ffffh sa1051100010xxx 310000h to 317fffh sa1061100011xxx 31 8000h to 31ffffh sa1071100100xxx 320000h to 327fffh sa1081100101xxx 32 8000h to 32ffffh sa1091100110xxx 330000h to 337fffh sa1101100111xxx 33 8000h to 33ffffh sa1111101000xxx 340000h to 347fffh sa1121101001xxx 34 8000h to 34ffffh sa1131101010xxx 350000h to 357fffh sa1141101011xxx 35 8000h to 35ffffh sa1151101100xxx 360000h to 367fffh sa1161101101xxx 36 8000h to 36ffffh sa1171101110xxx 370000h to 377fffh sa1181101111xxx 37 8000h to 37ffffh
mb84vd23481fj- 70 12 (continued) bank sector sector address address range bank address word mode a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank d sa1191110000xxx 380000h to 387fffh sa1201110001xxx 38 8000h to 38ffffh sa1211110010xxx 390000h to 397fffh sa1221110011xxx 39 8000h to 39ffffh sa1231110100xxx 3a0000h to 3a7fffh sa1241110101xxx 3a 8000h to 3affffh sa1251110110xxx 3b0000h to 3b7fffh sa1261110111xxx 3b 8000h to 3bffffh sa1271111000xxx 3c0000h to 3c7 fffh sa1281111001xxx 3c 8000h to 3cffffh sa1291111010xxx 3d0000h to 3d7 fffh sa1301111011xxx 3d 8000h to 3dffffh sa1311111100xxx 3e0000h to 3e7fffh sa1321111101xxx 3e 8000h to 3effffh sa1331111110xxx 3f0000h to 3f7fffh sa1341111111000 3f8000h to 3f8fffh sa1351111111001 3f9000h to 3f9fffh sa1361111111010 3fa000h to 3fa fffh sa1371111111011 3fb000h to 3fb fffh sa1381111111100 3fc000h to 3fcfffh sa1391111111101 3fd000h to 3fdfffh sa1401111111110 3fe000h to 3fe fffh sa1411111111111 3ff000h to 3f ffffh
mb84vd23481fj- 70 13 sector group addresses sector group a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 0000000000 sa0 sga1 0000000001 sa1 sga2 0000000010 sa2 sga3 0000000011 sa3 sga4 0000000100 sa4 sga5 0000000101 sa5 sga6 0000000110 sa6 sga7 0000000111 sa7 sga8 00000 01 xxx sa8 to sa10 10 11 sga9 00001 xxxxx sa11 to sa14 sga10 00010 xxxxx sa15 to sa18 sga11 00011 xxxxx sa19 to sa22 sga12 00100 xxxxx sa23 to sa26 sga13 00101 xxxxx sa27 to sa30 sga14 00110 xxxxx sa31 to sa34 sga15 00111 xxxxx sa35 to sa38 sga16 01000 xxxxx sa39 to sa42 sga17 01001 xxxxx sa43 to sa46 sga18 01010 xxxxx sa47 to sa50 sga19 01011 xxxxx sa51 to sa54 sga20 01100 xxxxx sa55 to sa58 sga21 01101 xxxxx sa59 to sa62 sga22 01110 xxxxx sa63 to sa66 sga23 01111 xxxxx sa67 to sa70 sga24 10000 xxxxx sa71 to sa74 sga25 10001 xxxxx sa75 to sa78 sga26 10010 xxxxx sa79 to sa82 sga27 10011 xxxxx sa83 to sa86 sga28 10100 xxxxx sa87 to sa90 sga29 10101 xxxxx sa91 to sa94 sga30 10110 xxxxx sa95 to sa98 sga31 10111 xxxxx sa99 to sa102 sga32 11000 xxxxx sa103 to sa106 sga33 11001 xxxxx sa107 to sa110 sga34 11010 xxxxx sa111 to sa114 sga35 11011 xxxxx sa115 to sa118 sga36 11100 xxxxx sa119 to sa122 sga37 11101 xxxxx sa123 to sa126 sga38 11110 xxxxx sa127 to sa130 sga39 11111 00 xxx sa131 to sa133 01 10 sga40 1111111000 sa134 sga41 1111111001 sa135 sga42 1111111010 sa136 sga43 1111111011 sa137 sga44 1111111100 sa138 sga45 1111111101 sa139 sga46 1111111110 sa140 sga47 1111111111 sa141
mb84vd23481fj- 70 14 flash memory autoselect codes legend: l = v il , h = v ih . see dc characteristics for voltage levels. *1 : outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *2 : a read cycle at address (ba) 01h outputs device code. when 227eh was output, this indicates that there will require two additional codes, called extended device codes. therefore the system may continue reading out these extended device codes at the address of (ba) 0eh, as well as at (ba) 0fh. type a 21 to a 12 a 6 a 3 a 2 a 1 a 0 code (hex) manufactures code ba l l l l l 04h device code ba l l l l h 227eh extended device code * 2 ba l h h h l 2202h ba l h h h h 2201h sector group protection sector group addresses l l l h l 01h* 1
mb84vd23481fj- 70 15 flash memory command definitions (continued) command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/reset 1 xxxh f0h read/reset 3 555h aah 2aah 55h 555h f0h ra* 5 rd* 9 autoselect 3 555h aah 2aah 55h (ba* 8 ) 555h 90h program 4 555h aah 2aah 55h 555h a0h pa* 6 pd* 10 program suspend 1ba* 8 b0h program resume 1ba* 8 30h chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa* 7 30h erase suspend 1ba* 8 b0h erase resume 1ba* 8 30h extended sector group protection * 2 4 xxxh 60h spa* 11 60h spa* 11 40h spa* 11 sd* 12 set to fast mode 3 555h aah 2aah 55h 555h 20h fast program * 1 2 xxxh a0h pa* 6 pd* 10 reset from fast mode * 1 2ba* 8 90h xxxh f0h* 4 query 1 (ba* 8 ) 55h 98h hiddenrom entry 3 555h aah 2aah 55h 555h 88h hiddenrom program * 3 4 555h aah 2aah 55h 555h a0h (hra* 13 ) pa* 6 pd* 10 hiddenrom exit * 3 4 555h aah 2aah 55h (hrba* 14 ) 555h 90hxxxh00h
mb84vd23481fj- 70 16 (continued) *1: this command is valid during fast mode. *2: this command is valid while reset = v id . *3: this command is valid during hiddenrom mode. *4: the data 00h is also acceptable. *5: ra = address of the memory location to be read *6: pa = address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. *7: sa = address of the sector to be erased. the combination of a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. *8: ba = bank address (a 21 , a 20 , a 19 ) *9: rd = data read from location ra during read operation. *10:pd = data to be programmed at location pa. data is latched on the rising edge of write pulse. *11:spa = sector group address to be protected. set sector group address and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0). *12:sd = sector group protection verify data. output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. *13:hra = address of the hiddenrom area: 000000h to 00007fh *14: hrba = bank address of the hiddenrom area (a 21 = a 20 = a 19 = v il ) notes : address bits a 21 to a 11 = x = h or l for all address commands except or program address (pa), sector address (sa), and bank address (ba), and sector group address (spa). bus operations are defined in n device bus operation. the system should generate the following address patterns: 555h or 2aah to addresses a 10 to a 0 both read/reset commands are functionally equivalent, resetting the device to the read mode. the command combinations not described in this table are illegal.
mb84vd23481fj- 70 17 n absolute maximum ratings *1: minimum dc voltage on input or i/o pins is C0.3 v. during voltage transitions, input or i/o pins may undershoot v ss to C1.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc f+0.3 v or v cc r+0.3 v. during voltage transitions, input or i/o pins may overshoot to v cc f+1.0 v or v cc r+1.0 v for periods of up to 5 ns. *2: minimum dc input voltage on reset pin is C0.5 v. during voltage transitions, reset pin may undershoot v ss to C2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (v in -v cc f or v cc r) does not exceed 9.0 v. maximum dc input voltage on reset pin is +13.0 v which may overshoot to +14.0 v for periods of up to 20 ns. *3: minimum dc input voltage on wp /acc pin is C0.5 v. during voltage transitions, wp /acc pin may undershoot vss to C2.0 v for periods of up to 20 ns. maximum dc input voltage on wp /acc pin is +10.5 v which may overshoot to +10.5 v for periods of up to 20 ns, when v cc f is applied. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max storage temperature tstg - 55 + 125 c ambient temperature with power applied t a - 30 + 85 c voltage with respect to ground all pins * 1 v in - 0.3 v cc f + 0.3 v v out - 0.3 v cc r + 0.3 v v cc f supply * 1 v cc f - 0.2 + 3.6 v v cc r supply * 1 v cc r - 0.2 + 3.6 v reset * 2 v in - 0.5 + 13.0 v wp /acc * 3 v in - 0.5 + 10.5 v parameter symbol value unit min max ambient temperature t a - 30 + 85 c v cc f supply voltages v cc f + 2.7 + 3.1 v v cc r supply voltages v cc r + 2.7 + 3.1 v
mb84vd23481fj- 70 18 n electrical characteristics 1. dc characteristics* 1, * 2, * 3 (continued) parameter symbol test conditions value unit min typ max input leakage current i li v in = v ss to v cc f, v cc rC1.0+1.0 m a output leakage current i lo v out = v ss to v cc f, v cc rC1.0+1.0 m a reset inputs leakage current i lit v cc f = v cc f max, reset = 12.5 v 35 a flash v cc active current (read) * 4 i cc1 fce f = v il , oe = v ih t cycle = 5 mhz 18 ma t cycle = 1 mhz 4 ma flash v cc active current (program/erase) * 5 i cc2 fce f = v il , oe = v ih 30ma flash v cc active current (read-while-program) * 8 i cc3 fce f = v il , oe = v ih 48ma flash v cc active current (read-while-erase) * 8 i cc4 fce f = v il , oe = v ih 48ma flash v cc active current (erase-suspend-program) i cc5 fce f = v il , oe = v ih 30ma wp /acc acceleration program current i acc v cc f = v cc f max, wp /acc = v acc max 20ma fcram v cc active current i cc1 r v cc r = v cc r max, ce1 r = v il , ce2r = v ih, v in = v ih or v il , i out = 0 ma t rc / t wc = min 25 ma t rc / t wc = 1 m s 3 flash v cc standby current i sb1 f v cc f = v cc f max, ce f = v cc f 0.3 v reset = v cc f 0.3 v, wp /acc = v cc f 0.3 v 1 5 m a flash v cc standby current (reset ) i sb2 f v cc f = v cc f max, reset = v ss 0.3 v, wp /acc = v cc f 0.3 v 1 5 m a flash v cc current (automatic sleep mode)* 6 i sb3 f v cc f = v cc f max, ce f = v ss 0.3 v reset = v cc f 0.3 v, wp /acc = v cc f 0.3 v v in = v cc f 0.3 v or v ss 0.3 v 1 5 m a fcram v cc standby current i sb1 r v cc r = v cc r max,ce1 r > v cc r C 0.2 v, ce2r > v cc rC 0.2 v, v in < 0.2 v or v cc r C 0.2 v 100 m a fcram v cc power down current i pds r v cc r = v cc r max, ce1 r > v cc r C 0.2 v, ce2r < 0.2 v sleep 10 m a i pdn r nap 60 m a i pd8 r 8m partial 70 m a
mb84vd23481fj- 70 19 (continued) *1 : all voltage are referenced to v ss . *2 : fcram dc characteristics are measured after following power-up timing. *3 : i out depends on the output load conditions. *4 : the i cc current listed includes both the dc operating current and the frequency dependent component. *5 : i cc active while embedded algorithm (program or erase) is in progress. *6 : automatic sleep mode enables the low power mode when address remain stable for 150 ns. *7 : applicable for only v cc applying. *8 : embedded alogorithm (program or erase) is in progress. (@5mhz) parameter symbol test conditions value unit min typ max input low level v il C0.3 0.5 v input high level v ih flash 2.0 v cc f+0.3 v fcram 2.2 v cc r+0.3 voltage for autoselect and sector protection (reset )* 7 v id 11.5 12.5 v voltage for wp /acc sector protection/unprotection and program acceleration v acc 8.5 9.0 9.5 v fcram output low level v ol v cc r = v cc r min, i ol = 1.0 ma 0.4 v fcram output high level v oh v cc r = v cc r min, i oh = C0.5 ma 2.2 v flash output low level v ol v cc f = v cc f min, i ol = 4.0 ma 0.45 v flash output high level v oh v cc f = v cc f min, i oh = C0.1 ma v cc fC0.4 v flash low v cc lock-out voltage v lko 2.3 2.4 2.5 v
mb84vd23481fj- 70 20 2. ac characteristics ? ce timing ? timing diagram for alternating fcram to flash parameter symbol condition value unit jedec standard min ce recover time ? t ccr ? 0ns ce hold time ? t chold ? 3ns ce1 r high to we invalid time for standby entry t chwx 10ns ce f t ccr t ccr ce1 r ce2r t ccr t ccr we t chwx t chold
mb84vd23481fj- 70 21 ? read only operations characteristics (flash) *: test conditionsC output load:1 ttl gate and 30 pf input rise and fall times: 5 ns input pulse levels: 0.0 v or v cc f timing measurement reference level input: 0.5v cc f output: 0.5v cc f parameter symbol condition value * unit jedec standard min max read cycle time t avav t rc 70ns address to output delay t avqv t acc ce f = v il oe = v il 70ns chip enable to output delay t elqv t ce foe = v il 70ns output enable to output delay t glqv t oe 30ns chip enable to output high-z t ehqz t df 25ns output enable to output high-z t ghqz t df 25ns output hold time from addresses, ce f or oe , whichever occurs first t axqx t oh 0ns reset pin low to read mode t ready 20s
mb84vd23481fj- 70 22 ? read operation timing diagram (flash) ? hardware reset/read operation timing diagram (flash) address address stable high-z high-z cef oe we outputs outputs valid t rc t acc t oe t df t ce t oh t oeh address cef reset outputs high-z outputs valid address stable t rc t acc t rh t rp t rh t ce t oh
mb84vd23481fj- 70 23 ? write / erase / program operations (flash) (continued) parameter symbol value unit jedec standard min typ max write cycle time t avav t wc 70 ?? ns address setup time t avwl t as 0 ?? ns address setup time to oe low during toggle bit polling ? t aso 12 ?? ns address hold time t wlax t ah 45 ?? ns address hold time from ce f or oe high during toggle bit polling ? t aht 0 ?? ns data setup time t dvwh t ds 30 ?? ns data hold time t whdx t dh 0 ?? ns output enable hold time read ? t oeh 0 ?? ns toggle and data polling 10 ?? ns ce f high during toggle bit polling ? t ceph 20 ?? ns oe high during toggle bit polling ? t oeph 20 ?? ns read recover time before write t ghwl t ghwl 0 ?? ns read recover time before write t ghel t ghel 0 ?? ns ce f setup time t elwl t cs 0 ?? ns we setup time t wlel t ws 0 ?? ns ce f hold time t wheh t ch 0 ?? ns we hold time t ehwh t wh 0 ?? ns write pulse width t wlwh t wp 35 ?? ns ce f pulse width t eleh t cp 35 ?? ns write pulse width high t whwl t wph 25 ?? ns ce f pulse width high t ehel t cph 25 ?? ns programming operation t whwh1 t whwh1 ? 6 ?m s sector erase operation * 1 t whwh2 t whwh2 ? 0.5 ? s v cc f setup time ? t vcs 50 ??m s rise time to v id * 2 ? t vidr 500 ?? ns rise time to v acc * 3 ? t vaccr 500 ?? ns voltage transition time * 2 ? t vlht 4 ??m s write pulse width * 2 ? t wpp 100 ??m s
mb84vd23481fj- 70 24 (continued) *1: this does not include preprogramming time. *2: this timing is for sector group protection operation. *3: this timing is for accelerated program operation. parameter symbol value unit jedec standard min typ max oe setup time to we active * 2 ? t oesp 4 ??m s ce f setup time to we active * 2 ? t csp 4 ??m s recover time from ry/by ? t rb 0 ?? ns reset pulse width ? t rp 500 ?? ns reset high level period before read ? t rh 200 ?? ns program/erase valid to ry/by delay ? t busy ?? 90 ns delay time from embedded output enable ? t eoe ?? 70 ns erase time-out time ? t tow 50 ?m s erase suspend transition time ? t spd ?? 20 m s
mb84vd23481fj- 70 25 ? write cycle (we control) (flash) notes : pa is address of the memory location to be programmed. pd is data to be programmed at word address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles out of four bus cycle sequence. address data cef oe we 3rd bus cycle data polling 555h pa a0h pd dq 7 d out d out pa t wc t as t ah t rc t ce t whwh1 t wph t wp t ghwl t ds t dh t df t oh t oe t cs t ch
mb84vd23481fj- 70 26 ? write cycle (ce f control) (flash) address data we oe cef 3rd bus cycle data polling 555h pa a0h pd dq 7 d out pa t wc t as t ah t whwh1 t cph t cp t ghel t ds t dh t ws t wh notes : pa is address of the memory location to be programmed. pd is data to be programmed at word address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles out of four bus cycle sequence.
mb84vd23481fj- 70 27 ? ac waveforms chip/sector erase operations (flash) address data v cc f cef oe we 555h 2aah 555h 555h 2aah sa* t wc t as t ah t cs t ghwl t ch t wp t ds t vcs t dh t wph aah 55h 80h aah 55h 10h/ 30h 30h for sector erase * : sa is the sector address for sector erase. addresses = 555h (word) for chip erase.
mb84vd23481fj- 70 28 ? ac waveforms for data polling during embedded algorithm operations (flash) * : dq 7 = valid data (the device has completed the embedded operation) . t oeh t ch t oe t ce t df t busy t eoe t whwh1 or 2 cef dq 7 dq 6 to dq 0 ry/by dq 7 dq 7 = valid data dq 6 to dq 0 = output flag dq 6 to dq 0 valid data oe we high-z high-z data data *
mb84vd23481fj- 70 29 ? ac waveforms for toggle bit during embedded algorithm operations (flash) t dh t oe t ce cef we oe dq 6 /dq 2 address ry/by data toggle data toggle data toggle data stop toggling output valid * t busy t oeh t oeh t oeph t aht t aht t aso t as t ceph * : dq 6 stops toggling (the device has completed the embedded operation).
mb84vd23481fj- 70 30 ? back-to-back read/write timing diagram (flash) cef dq we address ba1 ba1 ba1 ba2 (555h) ba2 (pa) ba2 (pa) oe valid output valid output valid output status valid intput valid intput t rc t rc t rc t rc t wc t wc t aht t as t as t ah t acc t ce t oe t oeh t wp t ghwl t ds t df t dh t df t ceph read command command read read read (a0h) (pd) note : this is example of read for bank 1 and embedded algorithm (program) for bank 2. ba1 : address corresponding to bank 1 ba2 : address corresponding to bank 2
mb84vd23481fj- 70 31 ? ry/by timing diagram during write/erase operations (flash) ? reset , ry/by timing diagram (flash) cef ry/by we rising edge of the last we signal t busy entire programming or erase operations t rp t rb t ready ry/by we reset
mb84vd23481fj- 70 32 ? temporary sector unprotection (flash) ? acceleration mode timing diagram (flash) unprotection period t vlht t vlht t vcs t vlht t vidr program or erase command sequence v cc f v id v ih we ry/by cef reset v ih wp/acc v cc f cef we ry/by t vlht program command sequence t vlht t vcs t vaccr vacc t vlht acceleration period
mb84vd23481fj- 70 33 ? extended sector group protection (flash) spax : sector group address to be protected spay : next sector group address to be protected time-out : time-out window = 250 m s (min) v cc f we oe cef reset t wc t wc t vlht t vidr t vcs time-out spax spax spay t wp t oe 60h 01h 40h 60h 60h data address a 6 , a 3 , a 2 , a 0 a 1
mb84vd23481fj- 70 34 n 32m fcram characteristics for mcp 1. fcram power down program key table* 1 basic key table available key table definition a 16 a 17 a 18 a 19 a 20 key mode select area select a 18 a 19 a 20 area lll bottom * 3 l h x reserved h l x reserved hhh top * 2 a 16 a 17 mode l l nap * 4 l h reserved hl8m partial h h sleep * 4, * 5 mode a 16 a 17 a 18 a 19 a 20 data retention area mode select area select nap l l x x x none 8m partial hllllbottom 8m only h l h h h top 8m only sleep h h x x x none *1 : the power down program can be performed one time after compliance of power-up timings and it should not be re-programmed after regular read or write. unspecified addresses, a 15 to a 0 , can be either high or low during the programming. the reserved key should not be used. *2 : top area is from the lowest address location. (i.e., a 20 to a 0 = l) *3 : bottom area is from the highest address location. (i.e., a 20 to a 0 = h) *4 : nap and sleep do not retain the data and area select is ignored. *5 : default state. power down program to this sleep mode can be omitted.
mb84vd23481fj- 70 35 2. ac characteristics ? read operation (fcram) *1 : the output load is 30 pf. *2 : the output load is 5 pf. *3 : the t ce is applicable if oe is brought to low before ce1 r goes low and is also applicable if actual value of both or either t aso or t clol is shorter than specified value. *4 : applicable only to a 0 and a 1 when both ce1 r and oe are kept at low for the address access. *5 : applicable if oe is brought to low before ce1 r goes low. *6 : the t aso , t clol (min) and t op (min) are reference values when the access time is determined by t oe . if actual value of each parameter is shorter than specified minimum value, t oe become longer by the amount of subtracting actual value from specified minimum value. for example, if actual t aso , t aso (actual), is shorter than specified minimum value, t aso (min), during oe control access (ie., ce1 r stays low), the t oe become t oe (max) + t aso (min) C t aso (actual). *7 : the t aso(abs) and t op(abs) is the absolute minimum value during oe control access. *8 : the t ax is applicable when both a 0 and a 1 are switched from previous state. *9 : if actual value of either t clol or t op is shorter than specified minimum value, both t olah and t olch become t rc (min) C t clol (actual) or t rc (min) C t op (actual). *10 : maximum value is applicable if ce1 r is kept at low. parameter symbol value unit notes min max read cycle time t rc 70 ns chip enable access time t ce 65ns*1,*3 output enable access time t oe 40ns*1 address access time t aa 65ns*1,*4 output data hold time t oh 5ns*1 ce1 r low to output low-z t clz 5ns*2 oe low to output low-z t olz 0ns*2 ce1 r high to output high-z t chz 20ns*2 oe high to output high-z t ohz 20ns*2 address setup time to ce1 r low t asc C5 ns *5 address setup time to oe t aso 25 ns *3,*6 t aso(abs) 10 ns *7 lb / ub setup time to ce1 r low t bsc C5 *5 lb / ub setup time to oe low t bso 10 address invalid time t ax 5ns*4,*8 address hold time from ce1 r low t clah 70 ns *4 address hold time from oe low t olah 45 ns *4,*9 address hold time from ce1 r high t chah C5 ns address hold time from oe high t ohah C5 ns lb / ub hold time from ce1 r high t chbh C5 lb / ub hold time from oe high t ohbh C5 ce1 r low to oe low delay time t clol 25 1000 ns *3,*6,*9,*10 oe low to ce1 r high delay time t olch 45 ns *9 ce1 r high pulse width t cp 12 ns oe high pulse width t op 25 1000 ns *6,*9,*10 t op(abs) 12 ns *7
mb84vd23481fj- 70 36 ? write operation (fcram) *1 : minimum value must be equal or greater then the sum of actual t cw (or t wp ) and t wrc (or t wr ). *2 : new write address is valid from either ce1 r or we is bought to high. *3 : the t oeh is specified from end of t wc (min). the t oeh (min) is a reference value when the access time is determined by t oe . if actual value, t oeh (actual) is shorter than specified minimum value, t oe become longer by the amount of subtracting actual value from specified minimum value. *4 : the t oeh (max) is applicable if ce1 r is kept at low and both we and oe are kept at high. *5 : the t oeh(abs) is the absolute minimum value if write cycle is termnated by we and ce1 r stays low. *6 : t ohcl (min) must be satisfied if read operation is not performed prior to write operation. in case oe is disabled after t ohcl (min), we low must be asserted after t rc (min) from ce1 r low. in other words, read operation is initiated if t ohcl (min) is not satisfied. *7 : applicable if ce1 r stays low after read operation. *8 : t cw and t wp is applicable if write operation is initiated by ce1 r and we , respectively. *9 : t wrc and t wr is applicable if write operation is terminated by ce1 r and we , respectively. the t wr (min) can be ignored if ce1 r is brought to high together or after we is brought to high. in such case, the t cp (min) must be satisfied. parameter symbol value unit notes min max write cycle time t wc 70 ns *1 address setup time t as 0ns*2 address hold time t ah 35 ns *2 ce1 r write setup time t cs 01000ns ce1 r write hold time t ch 01000ns we setup time t ws 0ns we hold time t wh 0ns lb and ub setup time t bs C5 ns lb and ub hold time t bh C5 ns oe setup time t oes 01000ns*3 oe hold time t oeh 25 1000 ns *3, *4 t oeh(abs) 12 ns *5 oe high to ce1 r low setup time t ohcl C5 ns *6 oe high to address hold time t ohah C5 ns *7 ce1 r write pulse width t cw 45 ns *1, *8 we write pulse width t wp 45 ns *1, *8 ce1 r write recovery time t wrc 10 ns *1, *9 we write recovery time t wr 10 1000 ns *1, *3, *9 data setup time t ds 15 ns data hold time t dh 0ns ce1 r high pulse width t cp 12 ns *9
mb84vd23481fj- 70 37 ? power down and power down program parameters (fcram) * : applicable to power down program. ? other timing parameters (fcram) *1 : it may write some data into any address location if t chwx is not satisfied. *2 : must satisfy t chh (min) after t c2lh (min). *3 : requires power down mode entry and exit after t c2hl . *4 : the input trasition time(t t ) at ac testing is 5 ns as shown in below. if actual t t is longer than 5 ns, it may violate ac specification of some timing parameters. ? ac test conditions (fcram) parameter symbol value unit note min max ce2r low setup time for power down entry t csp 10 ns ce2r low hold time after power down entry t c2lp 70 ns ce1 r high hold time following ce2r high after power down exit (sleep mode only) t chh 350 m s ce1 r high setup time following ce2r high after power down exit (except for sleep mode) t chhn 1 m s ce1 r high setup time following ce2r high after power down exit t chs 10 ns ce1 r high to pe low setup time t eps 70 ns * pe power down program pulse width t ep 70 ns * pe high to ce1 r low hold time t eph 70 ns * address setup time to pe high t eas 15 ns * address setup time from pe high t eah 0ns* parameter symbol value unit note min max ce1 r high to oe invalid time for standby entry t chox 10 ns ce1 r high to we invalid time for standby entry t chwx 10 ns *1 ce2r low hold time after power-up t c2lh 50 ms *2 ce2r high hold time after power-up t c2hl 50 ms *3 ce1 r high hold time following ce2r high after power-up t chh 350 ms *2 input transition time t t 125ns*4 description symbol test setup value unit note input high level v ih v cc r = 2.7 v to 3.1 v 2.3 v input low level v il v cc r = 2.7 v to 3.1 v 0.4 v input timing measurement level v ref v cc r = 2.7 v to 3.1 v 1.3 v input transition time t t between v il and v ih 5ns
mb84vd23481fj- 70 38 ? read timing #1 (oe control access) (fcram) note : ce2r, pe and we must be high for entire read cycle. either or both lb and ub must be low when both ce1 r and oe are low. t ce valid data output address ce1 r dq (output) lb / ub t ohz t ohz t oe t rc t olz t olz t ohah t op address valid t aso t oe valid data output address valid t clol t rc t oh t oh t ohah t aso t olch oe t bso t bso t ohbh t ohbh
mb84vd23481fj- 70 39 ? read timing #2 (ce1 r control access) (fcram) note : ce2r, pe and we must be high for entire read cycle. either or both lb and ub must be low when both ce1 r and oe are low. t ce t ce valid data output address ce1 r dq (output) oe t chz t chz t rc t clz t chah t cp address valid t asc valid data output address valid t asc t chah t clz t oh t oh t rc lb / ub t bsc t bsc t chbh t chbh
mb84vd23481fj- 70 40 ? read timing #3 (address access after oe control access) (fcram) note : ce2r, pe and we must be high for entire read cycle. either or both lb and ub must be low when both ce1 r and oe are low. valid data output address (a 2 to a 0 ) ce1 r dq (output) oe t ohz t oe t rc t olz t olah address valid t ax valid data output address valid t rc t oh t oh t ohah t aso t aa address (a 20 to a 3 ) address valid address valid (no change) lb / ub t bso t ohbh
mb84vd23481fj- 70 41 ? read timing #4 (address access after ce1 r control access) (fcram) note : ce2r, pe and we must be high for entire read cycle. either or both lb and ub must be low when both ce1 r and oe are low. t aa t ce valid data output address (a 2 to a 0 ) ce1 r dq (output) oe t chz t rc t clz t ax address valid valid data output address valid t asc t chah t oh t oh t rc t clah address (a 20 to a 3 ) address valid address valid (no change) lb / ub t bsc t chbh
mb84vd23481fj- 70 42 ? write timing #1 (ce1 r control) (fcram) note : ce2r and pe must be high for write cycle. t as valid data input address ce1 r dq (input) we t dh t ds t wc t wrc t ws t cw t wh ub , lb t bh t bs address valid t as t ah t ws t bs oe t ohcl
mb84vd23481fj- 70 43 ? write timing #2-1 (we control,single write operetion) (fcram) note : ce2r and pe must be high for write cycle. t as address we ce1 r t wc t cs t wp ub , lb t bs address valid t as t ah t wr t bh t cp valid data input dq (input) t dh t ds oe t oes t ohcl t ohah t ohz t ch t ohbh
mb84vd23481fj- 70 44 ? write timing #2-2 (we control,continuous write operetion) (fcram) note : ce2r and pe must be high for write cycle. t as address we ce1 r t wc t cs t wp ub , lb address valid t as t ah t wr t bh t bs valid data input dq (input) t dh t ds oe t oes t ohcl t ohah t ohz t bs t bh
mb84vd23481fj- 70 45 ? read / write timing #1-1 (ce1 r control) (fcram) note : write address is valid from either ce1 r or we of last falling edge. read data output address ce1 r dq we t wc t cw oe t ohcl ub , lb t bs t chah t cp write address t as t ah write data input t ds t chz t oh t wrc t clol t bh t asc read address t ws t wh t ws t wh t dh t olz t chbh t bso
mb84vd23481fj- 70 46 ? read / write timing #1-2 (ce1 r control) (fcram) note : the t oeh is specified from the time satisfied both t wrc and t wr (min). read data output address ce1 r dq we t rc t cp t ws oe t wh t ohcl t oeh ub , lb t bh t bs write address t chah t wrc (min) write data input t dh t oh t as t ws read address t chz t clz t ce t asc t wh t wrc t bsc t chbh
mb84vd23481fj- 70 47 ?read(oe control) / write(we control) timing #2-1 (fcram) note : ce1 r can be tied to low for we and oe controlled operation. when ce1 r is tied to low, output is exclusively controlled by oe . t wr read data output address ce1 r dq we t wc t wp oe t oes ub , lb t bs write address t as t ah write data input t dh t ds t ohz t oh low t oeh t bh t aso t ohah read address t olz t ohbh t bso
mb84vd23481fj- 70 48 ? read(oe control) / write(we control) timing #2-2 note : ce1 r can be tied to low for we and oe controlled operation. when ce1 r is tied to low, output is exclusively controlled by oe . ? power down program timing (fcram) note : ce2r must be high for power down programming. any other inputs not specified above can be either high or low. read data output address ce1 r dq we low oe t oes t oeh ub , lb t bh write address write data input t dh t oh t as read address valid t ohz t olz t oe t ohah t aso t rc t wr t ohbh t bs t bso t eps ce1 r pe t ep t eph t eas address (a 20 to a 16 ) key t eah
mb84vd23481fj- 70 49 ? power down entry and exit timing (fcram) note : this power down mode can be also used for power-up #2 below except that t chhn can not be used at power- up timing. ? power-up timing #1 (fcram) note : the t c2lh specifies after v cc r reaches specified minimum level. ? power-up timing #2 (fcram) note : the t c2hl specifies from ce2r low to high transition after v cc r reaches specified minimum level. ce1 r must be brought to high prior to or together with ce2r low to high transition. t csp ce1 r power down entry ce2r t c2lp t chh (t chhn ) power down mode power down exit t chs dq high-z t c2lh ce1 r v cc r v cc r min 0 v ce2r t chh t chs t c2hl ce1 r v cc r v cc r min 0 v ce2r t chh t chs t csp t c2lp t c2hl
mb84vd23481fj- 70 50 ? standby entry timing after read or write (fcram) note : both t chox and t chwx define the earliest entry timing for standby mode. if either of timing is not satisfied, it takes t rc (min) period from either last address transition of a 1 and a 0 , or ce1 r low to high transition. n erase and programming performance (flash) note : typical erase conditions t a = + 25c, vccf_1 & vccf_2 = 2.9 v typical program conditions t a = + 25c, vccf_1 & vccf_2 = 2.9 v data= checker parameter value unit remarks min typ max sector erase time 0.5 2 s excludes programming time prior to erasure word programming time 6 100 m s excludes system-level overhead chip programming time 25.2 95 s excludes system-level overhead erase/program cycle 100,000 cycle t chox ce1 r oe we active (read) standby active (write) standby t chwx
mb84vd23481fj- 70 51 3. data retention low v cc r characteristics (fcram) * : 2.0 v v ih v cc r + 0.3 v ? data retention timing parameter symbol test conditions value unit min max v cc r data retention supply voltage v dr ce1 r = ce2r 3 v cc r C 0.2 v or ce1 r = ce2r = v ih 2.1 3.1 v v cc r data retention supply current i dr 2.1 v v cc r 2.7 v, v in = v ih * or v il , ce1 r = ce2r = v ih *, i out = 0 ma 1.5ma i dr1 2.1 v v cc r 2.7 v, v in 0.2 v or v in 3 v cc r C 0.2 v, ce1 r = ce2r 3 v cc r C 0.2 v, i out = 0 ma 100 m a data retention setup time t drs 2.7 v v cc r 3.1 v at data retention entry 0 ns data retention recovery time t drr 2.7 v v cc r 3.1 v after data retention 200 ns v cc r voltage transition time d v/ d t0.2v/ m s d v/ d t ce1 r t drr data retention mode t drs v cc r- 0.2 v or v ih( * min v cc r 2.7 v 3.1 v 0.4 v 2.1 v v ss d v/ d t ce2r data bus must be in high-z at data retention entry. * : 2.0 v v ih v cc r + 0.3 v
mb84vd23481fj- 70 52 n pin capacitance note : test conditions t a = + 25c, f = 1.0 mhz n handling of package please handle this package carefully since the sides of package create acute angles. n caution ? the high voltage (v id ) cannot apply to address pins and control pins except reset . exception is when autoselect and sector group protect function are used, then the high voltage (v id ) can be applied to reset . ? without the high voltage (v id ) , sector group protection can be achieved by using extended sector group protection command. parameter symbol test setup value unit typ max input capacitance c in v in = 0 11 14 pf output capacitance c out v out = 0 12 16 pf control pin capacitance c in2 v in = 0 14 16 pf wp /acc pin capacitance c in3 v in = 0 21.5 26 pf
mb84vd23481fj- 70 53 n ordering information mb84vd23481 fj -70 pbs device number/description 64 mega-bit (4 m 16-bit) dual operation flash memory 3.0 v-only read, program, and erase 32 mega-bit (2 m 16-bit) fcram pa c k a g e t y p e pbs = 65-ball fbga speed option see product selector guide device revision
mb84vd23481fj- 70 54 n package dimension 65-ball plastic fbga (bga-65p-m01) dimensions in mm (inches). note: the values in parentheses are reference values. c 2001 fujitsu limited b65001s-c-1-2 9.00 0.10(.354 .004) 9.00 0.10 (.354 .004) index-mark area 0.10(.004) 0.39 0.10 (.015 .004) (stand off) .047 C .004 +.006 C 0.10 +0.15 1.19 (seated height) a b c d e f g h j k 1 2 3 4 5 6 7 8 9 10 65- ? .018 C .002 +.004 C 0.05 +0.10 65- ? 0.45 m 0.08(.003) 0.20(.008) sa s s 0.80(.031) 0.40(.016) ref ref 0.80(.031) ref ref 0.40(.016) a b sa s 0.10(.004) b s 0.20(.008) b index ball
mb84vd23481fj- 70 fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-partys intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0309 ? fujitsu limited printed in japan

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